parMERASA Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

International audienceEngineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-performance with timing-predictable execution. parMERASA will provide a timing analyzable system of parallel hard real-time applications running on a scalable multicore processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelizing hard real-time programs to run on predictable multi-/many-core processors. We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores, and techniques for predictable multi-core designs with up to 64 cores

Performanceanalyse und plattformspezifische Optimierungen am Beispiel des Grid-ALU-Prozessors

Sequentielle Programme können nicht vom Trend zu immer mehr Prozessorkernen profitieren. Zur Beschleunigung dieser Programme bedarf es neuer Architekturen. Ein Beispiel ist der Grid-ALU-Prozessor (GAP). Er ähnelt einer superskalaren Architektur, bei der eine dreidimensionale Struktur aus Funktionseinheiten zur Ausführung verwendet wird. Um bereits kompilierte Programme für die Ausführung auf dem GAP zu optimieren, kann der Post-Link-Optimierer GAPtimize verwendet werden. Dieses Tool unterstützt plattformspezifische Optimierungen, mit denen die Ausführungsgeschwindigkeit auf dem GAP durch Abschwächung negativer Einflussfaktoren erhöht werden kann. Mit einer automatischen Suche im Parameterraum werden Konfigurationen für den GAP ermittelt, die ein optimales Verhältnis aus Hardwareaufwand und Ausführungsgeschwindigkeit aufweisen. Diese Suche wird auf die Code-Optimierungen ausgedehnt. Durch die Verwendung von GAPtimize können signifikant bessere Ergebnisse erreicht werden.A trend towards many-core processor designs is evident to make use of the quickly growing resources on a chip available for processor designs. Novel architectures are developed to also accelerate sequential legacy programs not being able to gain any profit from multiple cores. The Grid ALU Processor (GAP) resembling a superscalar processor with a three dimensional execution unit is used in this work as example. To exploit its features without the need of rewriting or even recompiling legacy applications for quicker execution on the GAP the post link optimizer GAPtimize is introduced. It supports platform specific optimizations to reduce properties of programs restraining GAP's performance. Each of these restraining forces is addressed by at least one optimization. In an automatic design space exploration, configurations for the GAP are worked out showing near-optimal effectiveness, so gaining the best performance from the hardware resources. The search is extended to code optimizations and it is demonstrated that GAPtimize can improve both performance and area effectiveness of the GAP

parMERASA Pattern Catalogue: Timing Predictable Parallel Design Patterns

The aim of this catalogue is to describe parallel design patterns and synchronization idioms suitable for the development of parallel software for embedded systems supporting WCET analysis. It is written in context of the parMERASA FP7 project. It represents the state of knowledge after 24 month of the project, where parallelization concepts have been developed for all industrial applications. This catalogue is the basis for the Pattern-supported Parallelisation Approach, which is a model-based approach for the transition from sequential code to parallel code. In the scope of parMERASA, a timing analyzable implementation for some parallel design patterns, which is called Timing-analyzable Algorithmic Skeletons (TAS), is being developed which will ease the implementation of the patterns. Also further timing predictable parallel design patterns and synchronization idioms might be developed or discovered in the remainder of the project, as well as the examples in currently available design patterns will be updated with lessons learned from the parallelization of industrial applications in the parMERASA project. In that case a second edition of this pattern catalogue will be published

User manual for the optimization and WCET analysis of software with timing analyzable algorithmic skeletons

We recently presented a parallelization approach based on parallel design patterns and leading to structured parallelism. The approach is applicable for the parallelization of sequential code parts of embedded hard real-time software. To reduce work effort it is necessary to rely on tool support. In this context, we here present software for the model-based and multi-objective optimization of a software model with a high degree of parallelism. In addition, we introduce the timing analyzable algorithmic skeletons (TAS) for the fast implementation of the optimized software model. To support the static WCET analysis with the OTAWA toolset, we developed a compact XML format to describe software with TAS instances. Such a model can then easily be translated into the OTAWA XML format representing parallel flow-facts. All software described in this technical report is available under an open source license